About: Terasic DE25-Standard Development Kit

Terasic DE25-Standard Development Kit improvement unit offers Altera Agilex 5 SoC FPGA with 138K LEs to convey 2.5x execution leap forward and high level capabilities, for example, 1GB DDR4 32-bit information transport, 64MB SDRAM, 8-channel ADC header, GPIO header, a HSMC high velocity connector, and dark and light smaller than expected LCD, and so on. A rich arrangement of information and result highlights, for example, vigorous switches, LEDs, seven-section shows, and generally utilized I/O connection points are incorporated to address the issues of educating and tests.

In addition, the DE25-Standard is armed with the advanced HDMI output port (1080P), a two-lane MIPI CSI / DSI connector for camera and display, and a composite RCA jack for surveillance camera. Developers can leverage the AI tensor block on the Agilex™ 5 FPGA, the MIPI CSI / DSI connector, HDMI output, and the composite RCA jack on the DE25-Standard to develop AI-related applications such as video processing and computer vision.

DE25-Standard:

FPGA: A5ED013BB32AE4S (138K LEs)
Dimension: 166 mm x 130 mm
Onboard USB-Blaster II
Support ASx4 Configure Mode with 128Mbits QSPI Flash
Board Management System
Power Monitor
Temperature Monitor
Auto fan Control
Optional Active Heatsink

FPGA side:

DDR4: 1GB DDR4 with 32-bit data bus (no ECC), shared with HPS.
SDRAM: 64MB SDRAM with 32-bit data bus (no ECC).
HDMI 1.4 Output Port (Support 1080P)
One 2-lanes MIPI Connector for Camera/Display
Composite video-In
24-bits audio codec: MIC-In, Line-In, and Line-Out
8-channel ADC with 2x5 header
IR TX/RX
One 3.3V 2x20 DE-GPIO Header
One HSMC connector with 4 transceivers.
User LED x10, Button x4, Slide Switch x10, 7-segment x6

HPS side:

MicroSD Socket
DDR4: 1GB DDR4 with 32-bit data bus (no ECC), shared with FPGA
Gigabit Ethernet PHY + RJ45
Two USB Host ports with USB Type-A connector
UART to USB Port
128x64 LCD
Accelerometer
LED x1, Button x1, Cold Reset Button
One 3.3V 1x6 GPIO Header