About: Huins VP1902-S Versal Premium SoC/ASIC Single FPGA Board

Huins VP1902-S Versal Premium SoC/ASIC Single FPGA Board offering large-capacity FPGA logic emulation and prototyping target equipped with one Versal Premium XCVP1902-2MSEVSVA6865. VP1902-S offers 2.2x more logic cells reaching 18.5 million logic cells.

Delivering maximum capacity and connectivity with rammable logic density and 2.4x higher I/O bandwidth, the VP1902 adaptive SoC leverages a universal architecture including programmable network-on-chip to outperform previous generations. Delivers up to 8.5x faster debugging performance compared to VU19P FPGAs.

As ASIC and SoC design complexity increases rapidly due to the rapid evolution of AI and Machine Learning-based chips, extensive validation of silicon and software prior to tape-out is essential. To meet these requirements, Huins seeks to provide the best, most efficient boards with proven FPGA technology and know-how that are recognized as the best in the country.

MFP-VP1902-S can be easily expanded with various functions through FMC+ Supports 3200MHz and 32GB memory.

It is possible to manufacture and verify desired expansion modules such as PCIe Gen5, CSI, DSI, USB3.0, DDR4, Ethernet, HDMI, VX1, etc., and remote download and control of Power/Reset/Config control is possible through USB.

Low skew, high-speed clocks are distributed by the clock buffer. The clock can use the clock output of the board's 4 oscillators.

Features:

XCVP1902-2MSEVSVA6865 XILINX VERSAL FPGA Chip mount
18.5 Million system logic cells, total 2,000 I/O
Dual ARM® Cortex®-A72 MPCore™, Dual ARM® Cortex™-R5F
DDR4 SODIMM x 2, Max. 3200MHz, 32GB x 2
Peripherals: Giga Eth, USB, SD, QSPI, UART
FMC+ x 8, QTH x 3, NVAF x 2, QSFP-DD x 2 Extension Connector
GTYP 64 Lane(8 Lane 8ea), GTM 32 Lane(8 Lane 4ea)
Clock Module (CLK 0~3) Clock Generator 6.25 ~ 400MHz
Supports up to 8 individually adjustable Vccos
User Daughter Module Support